ELEC ENG 3088/7088 Computer Architecture
Assignment — RISC-V RV64F ISS — Stage 2
Your task for this assignment is to extend your RV64I ISS from Stage 1 with:
• "RV64F" Extension for Single-Precision Floating-Point, Version 2.2, defined in Chapter 20 of The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture, version 20240411,
• Create a comprehensive test suite for RV64F.
The RISC-V “F” Extension specification defines single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard (ANSI/IEEE Std 754-2008, IEEE Standard for Floating- Point Arithmetic, 2008). The “F” extension depends on the “Zicsr” extension for control and status register access. For this stage of the assignment, you should implement all registers and instructions defined in the “F” extension. The required instructions provided by “Zicsr” extension is provided as part of the skeleton in processorZicsr.cpp.
You should implement all the instructions listed in Chapter 34 for RV32F and RV64F, with all instruction implementations in processorF.cpp. The RV64F instructions must only be valid when
We have provided an extended command handler that implements the following commands, in addition to those provided for Stage 1:
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Command
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Operation performed
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csr num
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Show the content of CSR num (num in hex). The value is displayed as 16 hex digits with leading 0s.
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csr num = value
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Set CSR num to value (num and value in hex).
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The following Zicsr extension instructions are provided:
• csrrw, csrrs, csrrwi
to implement the RV32F/RV64F pseudo-instructions:
• frcsr, frrm, frflags, fscsr, fsrm, fsflags, fsrmi, fsflagsi.
The floating-point control and status registers are listed in Table 71 of the manual and described here:
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Number
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Privilege
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Name
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Defined in process.h
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Description
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0x001
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Read/Write
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fflags
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CSR_NUM_FFLAGS
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Floating-Point Accrued Exceptions.
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0x002
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Read/Write
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frm
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CSR_NUM_FRM
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Floating-Point Dynamic Rounding Mode.
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0x003
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Read/Write
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fcsr
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CSR_NUM_FCSR
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Floating-Point Control and Status Register.
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The second task of the stage is to create a comprehensive test suite for RV64F. The tests should be created in tests/instructionF_tests/ using by creating a series of instruction tests. A sample instructionF_test_frcsr.s is provided that utilizes macros TEST_INIT, TEST_EXPECT, TEST_FAIL and TEST_END. These macros must be used in each of your test scripts and are defined in test_defines.h. Your test suite should check for all possible implementation errors of the RV64F instructions.
Please keep an eye on the discussion forum on the course web site. We will answer any questions for clarification of requirements that arise there. We will also announce incremental releases of a test suite for this stage.
You must extend your program from Stage 1 and submit via the GitHub classroom listed on the assignment page. We will use a submission script that will check your submission, make your ISS, and run it with several test cases. Compliance with this development process will count toward the assessment of the assignment.
For the submission deadline, please refer to the course page on MyUni. There are two stages for the Assignment worth 20% of the course.
Your work for Stage 2 will be assessed based on the following criteria, with points awarded out of 1000:
• Program builds via supplied Makefile and completes all Stage 1 tests — 100 points
• Program passes student created test cases — 100 points
• Correct execution, based on the number of course test cases that pass — 400 points
• Comprehensive set of test cases, based on the number of errors picked up — 300 points
• Shortest set Stage 2 test cases, based on line count of *.s, provided all errors are picked up — 100 points
The points for the Stage 2 assignment will comprise 10% of your final assessment for the course. For the submission deadline, please refer to the course page on MyUni.